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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 1 . 5 m h z , 1 a s y n c h r o n o u s b u c k r e g u l a t o r f e a t u r e s g e n e r a l d e s c r i p t i o n 1a output current wide 2.7v~6.0v input voltage fixed 1.5mhz switching frequency low dropout operating at 100% duty cycle 25 m a quiescent current integrate synchronous rectifier 0.6v reference voltage c u r r e n t - m o d e o p e r a t i o n w i t h i n t e r n a l c o m p e n s a t i o n - stable with ceramic output capacitors - fast line transient response short-circuit protection over-temperature protection with hysteresis available in sot-23-5/tsot-23-5a packages lead free and green devices available (rohs compliant) apw7104 is a 1.5mhz high efficiency monolithic synchro- nous buck regulator. design with current mode scheme, the apw7104 is stable with ceramic output capacitor. in- put voltage from 2.7v to 6.0v makes the apw7104 ideally suited for single li-ion battery powered applications. 100% duty cycle provides low dropout operation, extending bat- tery life in portable electrical devices. the internally fixed 1.5mhz operating frequency allows the using of small surface mount inductors and capacitors. the synchro- nous switches included inside increase the efficiency and eliminate the need of an external schottky diode. the apw7104 is available in sot-23-5/tsot-23-5a packages. s i m p l i f i e d a p p l i c a t i o n c i r c u i t a p p l i c a t i o n s hd stb bt mouse pnd instrument portable instrument vin gnd 2 run 1 fb 5 apw 7104 sw 3 v in v out c 2 10 m f ( mlcc ) l 1 2 . 2 m h c 1 4 . 7 m f ( mlcc ) r 2 4 r 1 c 3 ( option ) p i n c o n f i g u r a t i o n 4 vin 5 fb gnd 2 sw 3 run 1 sot - 23 - 5 / tsot - 23 - 5 a ( top view ) apw 7104
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v in input bias supply voltage ( vin to gnd) - 0.3 ~ 7 v run, fb, sw to gnd voltage - 0.3 ~ v in +0.3 v p d power dissipation internally limited w maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature , 10 seconds 26 0 o c n o t e 1 : a b s o l u t e m a x i m u m r a t i n g s a r e t h o s e v a l u e s b e y o n d w h i c h t h e l i f e o f a d e v i c e m a y b e i m p a i r e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y . t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in f ree a ir (note 2) tsot - 23 - 5a sot - 23 - 5 220 250 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. symbol parameter range unit v in input bias supply voltage ( vin to gnd) 2.7 ~ 6 v v out converter output voltage 0.6 ~ v in v i out converter output current 0 ~ 1 a l1 converter output inductor 1.0 ~ 10 m h c in converter input capacitor 4.7 ~100 m f c out c onverter output capacitor 4.7 ~100 m f t a ambient temperature - 40 ~ 85 o c t j junction temperature - 4 0 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) n o t e 3 : r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t apw 7104 handling code temperature range package code assembly material apw 7104 bt : w 04 x x - date code package code bt : tsot - 23 - 5 a b : sot - 23 - 5 operating ambient temperature range i : - 40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw 7104 b : w 04 x x - date code
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 3 e l e c t r i c a l c h a r a c t e r i s t i c s apw 7104 symbol parameter test conditions min . typ . max . unit supply voltage and current v in input voltage range 2.7 - 6 v i dd quiescent current v fb = 0.66v - 25 40 m a i sd shutdown input current run = gnd - - 0.5 m a power - on - reset (por) and locko ut voltage thresholds uvlo threshold 2.1 2.35 2.6 v uvlo hysteresis - 0.1 - v reference voltage v ref reference voltage v in =2.7v~6v, t a = - 40~85 o c 0.588 0.6 0.612 v output voltage accuracy 0a < i out < 1a - 2.5 - +2.5 % i fb fb input current - 50 - 50 na internal power mosfets f sw switching frequency v fb = 0.6v 1.2 1.5 1.8 mhz foldback frequency v fb = 0.1v - 210 - khz foldback threshold voltage on fb v fb falling - 0.2 - v foldback hysteresis - 50 - mv r p - fet high side n - fet switch on r esis tance i sw =200ma - 0.28 - w r n - fet low side p - fet switch on r esistance i sw =200ma - 0.25 - w minimum on - time - - 100 ns maximum duty cycle - - 100 % protection i lim maximum inductor current - limit i p - fet , 2. 7 v ?? v i n ?? 6v 1.4 1.6 - a t otp over - temperature protection t j rising - 150 - over - temperature protection hysteresis t j falli ng - 30 - c start - up and shutdown t ss soft - start duration (note 4) - 0.7 - ms run input high threshold v in = 2.7v~6v - - 1 v run input low threshold v in = 2.7v~6v 0.4 - - v run leakage curren t v run = 5v, v in = 5v - 1 - 1 m a u n l e s s o t h e r w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v i n = 3 . 6 v a n d t a = 2 5 o c . n o t e 4 : g u a r a n t e e b y d e s i g n , n o t p r o d u c t i o n t e s t .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 4 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( r e f e r t o t h e a p p l i c a t i o n c i r c u i t i n t h e s e c t i o n ? t y p i c a l a p p l i c a t i o n c i r c u i t s ? , v i n = 3 . 6 v , v o u t = 1 . 8 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d ) 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 efficiency vs. load current e f f i c i e n c y ( % ) load current, i out (a) v out = 1.8v l = 2.2 h c out = 10 f v in =5v v in =3.3v efficiency vs. load current e f f i c i e n c y ( % ) load current, i out (a) 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 v out = 1.2v l = 2.2 h c out = 10 f v in =5v v in =3.3v o n r e s i s t a n c e ( w ) supply voltage, v in (v) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 2 2.5 3 3.5 4 4.5 5 5.5 6 supply voltage vs. on resistance r n-fet r p-fet q u i e s c e n t c u r r e n t , i d d ( a ) supply voltage v.s. quiescent current supply voltage, v in (v) 0 5 10 15 20 25 30 35 40 2 2.5 3 3.5 4 4.5 5 5.5 6 r e f e r e n c e v o l t a g e , v r e f ( v ) supply voltage v.s. reference voltage supply voltage, v in (v) 0.55 0.56 0.57 0.58 0.59 0.6 0.61 0.62 0.63 0.64 0.65 2 2.5 3 3.5 4 4.5 5 5.5 6
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 5 o p e r a t i n g w a v e f o r m s ( r e f e r t o t h e a p p l i c a t i o n c i r c u i t i n t h e s e c t i o n ? t y p i c a l a p p l i c a t i o n c i r c u i t s ? , v i n = 3 . 6 v , v o u t = 1 . 8 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d ) load transient response 300ma 2 1 v out ,100mv/div, ac i out , 0.5a/div, dc 1a l=2.2 h, v in =5v, v out =1.8v, c out =10 f time: 100 s/div normal operation 2 1 v out, 200mv/div,ac v in, 0.5v/div 1.5v 2.5v i out = 100ma time: 500ns/div 3 i l , 500mv/div, dc v out ,20mv/div, ac v sw ,2v/div, dc l=2.2 h, v in =5v, v out =1.2v, c out =10 f 3 1 2 soft start v out ,1v/div, dc i in , 200ma/div l=2.2 h, v in =5v, c out =10 f time: 100 s/div v run
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 6 p i n d e s c r i p t i o n pin no. name f unction 1 run enable control input. forcing this pin above 1.0v enables the device. forcing this pin below 0. 4 v shuts it down. in shutdown, all functions are disabled to decrease the supply current below 0.5 m a. do not leave run pin floatin g. 2 gnd power and signal ground. 3 sw switch node connected to inductor. this pin connects to the drains of the internal main and synchronous power mosfets switches. 4 vin device and converter supply pin . must be closely decoupled to gnd with a 4.7 m f o r greater ceramic capacitor. 5 fb feedback inpu t pin . the b uck regulator senses feedback voltage via fb and regulates the fb voltage at 0 .6 v. connecting fb with a resistor - divider from the output sets the output voltage of the b uck converter. b l o c k d i a g r a m oscillator logic control sw over- temperature protection v ref 0.6v eamp comp i cmp soft- start error amplifier zero- crossing comparator current -limit slope compensation vin current sense amplifier shutdown control ? fb run gnd gate driver
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 7 t y p i c a l a p p l i c a t i o n c i r c u i t vin gnd 2 run 1 fb 5 apw 7104 sw 3 v in 2 . 7 ~ 6 v v out 0 . 6 v ~ v in 0 ~ 1 a l 1 2 . 2 m h r 2 4 r 1 c 3 ( option ) c 1 4 . 7 m f ( mlcc ) c 2 10 m f ( mlcc ) i in r 1 1 m w is recommended r 2 200 k w is recommended c 1 closed to ic . less than 2 mm is recommended .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 8 f u n c t i o n d e s c r i p t i o n main control loop the apw7104 is a constant frequency, synchronous rec- tifier and current-mode switching regulator. in normal operation, the internal p-channel power mosfet is turned on each cycle. the peak inductor current at which icmp turn off the p-fet is controlled by the voltage on the comp node, which is the output of the error amplifier (eamp). an external resistive divider connected between v out and ground allows the eamp to receive an output feedback voltage v fb at fb pin. when the load current increases, it causes a slightly decrease in v fb relative to the 0.6v reference, which in turn causes the comp volt- age to increase until the average inductor current matches the new load current. under-voltage lockout an under-voltage lockout function prevents the device from operating if the input voltage on vin is lower than approxi- mately 1.8v. the device automatically enters the shut- down mode if the voltage on vin drops below approxi- mately 1.8v. this under-voltage lockout function is imple- mented in order to prevent the malfunctioning of the converter. soft-start the apw7104 has a built-in soft-start to control the out- put voltage rise during start-up. during soft-start, an in- ternal ramp voltage, connected to the one of the positive inputs of the error amplifier, raises up to replace the ref- erence voltage (0.6v typical) until the ramp voltage reaches the reference voltage. then, the voltage on fb regulated at reference voltage. enable/shutdown driving run to the ground places the apw7104 in shut- down mode. when in shutdown, the internal power mosfets turn off, all internal circuitry shuts down and the quiescent supply current reduces to 0.5 m a maximum. pulse frequency modulation mode (pfm) the apw7104 is a fixed frequency, peak current mode pwm step-down converter. at light loads, the apw7104 will automatically enter in pulse frequency mode opera- tion to reduce the dominant switching losses. in pfm operation, the inductor current may reach zero or reverse on each pulse. a zero current comparator turn off the n- fet, forcing dcm operation at light load. these controls get very low quiescent current, help to maintain high effi- ciency over the complete load range. slope compensation and inductor peak current the apw7104 is a peak current mode pwm step down converter. to prevent sub-harmonic oscillations, the apw7104 sense the peak current and add slope com- pensation to stable the converter. it is accomplished in- ternally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak cur- rent for duty cycles > 40%. however, the apw7104 uses a special scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. adaptive shoot-through protection the gate driver incorporates adaptive shoot-through pro- tection to high-side and low-side mosfets from con- ducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off the low-side mosfet, the internal lgate voltage is monitored until it is below 1.5v threshold, at which time the ugate is released to rise after a constant delay. during turn-off the high-side mosfet, the ugate voltage is also monitored until it is above 1.5v threshold, at which time the lgate is released to rise after a con- stant delay. dropout operation as the input supply voltage decreases to a value ap- proaching the output voltage, the duty cycle increases toward the maximum on time. further, reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. the input voltage minus the voltage drop will determine the output voltage across the p-fet and the inductor.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) dropout operation (cont.) an important detail to remember is that on resistance of p-fet switch will increase at low input supply voltage. therefore, the user should calculate the power dissipa- tion when the apw7104 is used at 100% duty cycle with low input voltage. over-temperature protection (otp) the over-temperature circuit limits the junction tempera- ture of the apw7104. when the junction temperature ex- ceeds 150 o c, a thermal sensor turns off the both power mosfets, allowing the devices to cool. the thermal sen- sor allows the converters to start a soft-start process and regulate the output voltage again after the junction tem- perature cools by 30 o c. the otp is designed with a 30 o c hysteresis to lower the average junction temperature (t j ) during continuous thermal overload conditions, in- creasing the lifetime of the device. short-circuit protection when the output is shortened to the ground, the frequency of the oscillator is reduced to about 210khz, 1/7 of the nominal frequency. this frequency foldback ensures that the inductor current has more time to decay, thereby pre- venting runaway. the oscillator?s frequency will progres- sively increase to 1.5mhz when v fb or v out rises above 0v.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 0 a p p l i c a t i o n i n f o r m a t i o n input capacitor selection b e c a u s e b u c k c o n v e r t e r s h a v e a p u l s a t i n g i n p u t c u r r e n t , a l o w e s r i n p u t c a p a c i t o r i s r e q u i r e d . t h i s r e s u l t s i n t h e b e s t i n p u t v o l t a g e f i l t e r i n g , m i n i m i z i n g t h e i n t e r f e r e n c e w i t h o t h e r c i r c u i t s c a u s e d b y h i g h i n p u t v o l t a g e s p i k e s . a l s o , t h e i n p u t c a p a c i t o r m u s t b e s u f f i c i e n t l y l a r g e t o s t a - b i l i z e t h e i n p u t v o l t a g e d u r i n g h e a v y l o a d t r a n s i e n t s . f o r g o o d i n p u t v o l t a g e f i l t e r i n g , u s u a l l y a 4 . 7 m f i n p u t c a p a c i - t o r i s s u f f i c i e n t . i t c a n b e i n c r e a s e d w i t h o u t a n y l i m i t f o r b e t t e r i n p u t - v o l t a g e f i l t e r i n g . c e r a m i c c a p a c i t o r s s h o w b e t t e r p e r f o r m a n c e b e c a u s e o f t h e l o w e s r v a l u e , a n d t h e y a r e l e s s s e n s i t i v e a g a i n s t v o l t a g e t r a n s i e n t s a n d s p i k e s c o m p a r e d t o t a n t a l u m c a p a c i t o r s . p l a c e t h e i n p u t c a p a c i t o r a s c l o s e a s p o s s i b l e t o t h e i n p u t a n d g n d p i n o f t h e d e v i c e f o r b e t t e r p e r f o r m a n c e . inductor selection for high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. especially at high-switching frequencies, the core material has a higher impact on efficiency. when using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. this needs to be considered when selecting the appropriate inductor. the inductor value de- termines the inductor ripple current. the larger the induc- tor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. conversely, larger inductor values cause a slower load transient response. a reasonable starting point for setting ripple current, d i l, is 40% of maximum output current. the rec- ommended inductor value can be calculated as below: l sw in out out i f v v 1 v l d ? ? ? ? ? - 3 i l(max) = i out(max) + 1/2 x d i l to avoid the saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current. output voltage setting in the adjustable version, the output voltage is set by a resistive divider. the external resistive divider is con- nected to the output, allowing remote voltage sensing as ? ? ? ? ? + = ? ? ? ? ? + = 2 r 1 r 1 6 . 0 2 r 1 r 1 v v ref out shown in ?typical application circuits?. a suggestion of maximum value of r2 is 200k w to keep the minimum current that provides enough noise rejection ability through the resistor divider. the output voltage can be calculated as below: output capacitor selection the current-mode control scheme of the apw7104 al- lows the use of tiny ceramic capacitors. the higher ca- pacitor value provides the good load transients response. ceramic capacitors with low esr values have the lowest output voltage ripple and are recommended. if required, tantalum capacitors may be used as well. the output ripple is the sum of the voltages across the esr and the ideal output capacitor. ? ? ? ? ? + ? ? ? ? ? - @ d out sw sw in out out out c f 8 1 esr l f v v 1 v v when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage char- acteristics of all the ceramics for a given value and size. v in v ou t i l n-fet sw i ou t c in c ou t i in esr p-fet i p-fet r2 200k w apw7104 fb gnd v out r1 1m w
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 1 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) thermal consideration in most applications, the apw7104 does not dissipate much heat due to its high efficiency. but, in applications where the apw7104 is running at high ambient tempera- ture with low supply voltage and high duty cycles, the heat dissipated may exceed the maximum junction tempera- ture of the part. if the junction temperature reaches ap- proximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the apw7104 from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to deter- mine whether the power dissipated exceeds the maxi- mum junction temperature of the part. the power dissi- pated by the part is approximated: p d @ i out 2 x (r p-fet x d+r n-fet x (1-d)) the temperature rise is given by: t r = (p d )( q ja ) where p d is the power dissipated by the regulator, d is duty cycle of main switch d = v out /v in the q ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. output capacitor selection (cont.) i lim i l i peak i out i p-fet d i l the maximum power dissipation on the device can be shown as follow figure: junction temperature ( o c) m a x i m u m p o w e r d i s s p a t i o n ( w ) -50 -25 0 25 50 75 100 125 150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 layout consideration for all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. if the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. the input capacitor should be placed close to the vin and gnd. connecting the capacitor and vin/gnd with short and wide trace without any via holes for good input voltage filtering. the distance between vin/gnd to capacitor less than 2mm respectively is recommended. 2. to minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the sw pin to minimize the noise coupling into other circuits. 3. the output capacitor should be place closed to con- verter vout and gnd. 4. since the feedback pin and network is a high imped- ance circuit the feedback network should be routed away from the inductor. the feedback pin and feed- back network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 5. a star ground connection or ground plane minimizes ground shifts and noise is recommended.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 2 layout consideration (cont.) a p w 7 1 0 4 l a y o u t s u g g e s t i o n r 1 r 2 l 1 v run v in v out c out c in gnd via to v out via to gnd fb sw
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 3 p a c k a g e i n f o r m a t i o n t s o t - 2 3 - 5 a s y m b o l min. max. 1.00 0.01 0.08 0.22 0.10 a a1 c d e e1 e e1 l millimeters b 0.30 0.50 0.95 bsc tsot-23-5a 0.30 0.60 0.037 bsc min. max. inches 0.039 0.000 0.028 0.035 0.003 0.009 0.012 0.024 0 0.004 a2 0.70 0.90 0.012 0.020 1.90bsc 0.075 bsc 0 8 0 8 1.40 1.80 2.60 3.00 2.70 3.10 0.106 0.122 0.055 0.071 0.102 0.118 note : 1. followed from jedec to-178 aa. 2. dimension d and e1 do not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 10 mil per side. 0.70 0.028 see view a c e 1 e d e e1 b a a 2 a 1 view a l seating plane gauge plane 0 . 2 5
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 4 p a c k a g e i n f o r m a t i o n s o t - 2 3 - 5 max. 0.057 0.051 0.024 0.006 0.009 0.020 0.012 l 0.30 0 e e1 e1 e d c b 0.08 0.30 0.60 0.012 0.95 bsc 1.90 bsc 0.22 0.50 0.037 bsc 0.075 bsc 0.003 min. millimeters s y m b o l a1 a2 a 0.00 0.90 sot-23-5 max. 1.45 0.15 1.30 min. 0.000 0.035 inches 8 0 8 0 b c e1 0 l view a 0 . 2 5 gauge plane seating plane a a 2 a 1 e d e e 1 see view a 1.40 2.60 1.80 3.00 2.70 3.10 0.122 0.071 0.118 0.102 0.055 0.106 note : 1. follow jedec to-178 aa. 2. dimension d and e1 do not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 10 mil per side.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 5 application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.30 1.75 ? 0.10 3.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tsot - 23 - 5a 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.0 min. 0.6+0.00 - 0 .40 3.20 ? 0.20 3.10 ? 0.20 1.50 ? 0.20 application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.30 1.75 ? 0.10 3.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sot - 23 - 5 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.0 min. 0.6+0.00 - 0.40 3.20 ? 0.20 3.10 ? 0.20 1.50 ? 0.20 (mm) d e v i c e s p e r u n i t c a r r i e r t a p e & r e e l d i m e n s i o n s package type unit quantity tsot - 23 - 5a tape & reel 3000 sot - 23 - 5 tape & reel 3000 a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 6 t a p i n g d i r e c t i o n i n f o r m a t i o n t s o t - 2 3 - 5 a user direction of feed s o t - 2 3 - 5 user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 7 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spe cified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - m a r . , 2 0 1 2 a p w 7 1 0 4 w w w . a n p e c . c o m . t w 1 8 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m c l a s s i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . )

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